The present invention relates to a semiconductor device fabrication technology; and, more particularly, to a method for fabricating an image sensor.
With respect to a semiconductor device fabrication technology requiring high integration and high-speed processes, it has been today actively researched on a method for achieving low resistance for a wiring material to decrease parasitic resistance.
For instance, in case of a multi-layer wiring, the grain size of Al constructing a metal line tends to be largely scaled and highly aligned to attain high reliability of the Al. Concurrently, it is also attempted to replace a commonly used material for the metal line with copper (Cu) to attain high reliability and to realize demands of low resistance. Also, in case of a conductive layer wiring process such as a gate electrode and a bit line, it is attempted to utilize silicide using titanium (Ti), cobalt (Co) and nickel (Ni) instead of using molybdenum (Mo), tungsten (W) to acquire a low temperature process required to a formation of devices highly integrated.
Also, image sensor is a device that receives and converts light from an external source to an electrical output. A photodiode is an area to which rays of light enter. A pnp junction or a pn junction in the photodiode forms an electron depletion area, which receives the light from the external source and further forms an electron hole pair (hereinafter referred as to EHP).
A unit pixel of a complementary metal-oxide semiconductor (CMOS) image sensor includes a single photodiode (hereinafter referred as to PD), a transfer transistor Tx, a reset transistor Rx, a drive transistor Dx, and a select transistor Sx. The transfer transistor Tx is closely located to the PD.
In a process for fabricating an image sensor with above 0.25 xcexcm technology, a salicide process is employed to reduce resistance of an active area and a polysilicon gate. However, metal layers implemented to the salicide process have a very high reflection ratio to light, and thus, it is impossible to apply the metal layers to a PD.
FIG. 1 is a diagram schematically illustrating a CMOS image sensor fabricated in accordance with a prior art.
Referring to FIG. 1, a gate oxide layer 12 and a gate electrode 13 are stacked on a selective area of a p-type epi layer 11. At one side of the gate electrode 13, a PD 15 is formed within an exposed area of the p-type epi layer 11, and a floating diffusion area 16 is formed within another exposed area of the p-type epi layer 11 at the other side of the gate electrode 13.
Herein, the gate electrode 13 is a polysilicon layer and a gate electrode of a transfer transistor.
Also, a salicide layer 17 is formed on each upper surface of the gate electrode 13 and the floating diffusion area 16.
In the above prior art, a salicide mask 18 is formed on the PD 15 to prevent the salicide layer from being formed on the PD 15.
At this time, a stepper used in the salicide mask 18 is an i-line equipment. However, with respect to overlay and critical dimension accuracies, it is difficult to accurately distinguish polysilicon closely located to the PD and subsequently put a mask on the polysilicon.
For example, in case that the PD is exposed due to misalignment of the salicide mask 18, a salicide layer is formed on the PD, and thus, a surface of the PD becomes unstabilized, further resulting in occurrence of dark signal. At this time, the dark signal occurs due to dark currents flowing from the PD to the floating diffusion area as electrons, generated even without inputs of incident lights due to the unstabilized surface, are stored into the PD.
Also, if the salicide mask 18 partially covers a portion of the gate electrode, the salicide layer is then prevented from being formed on the transfer transistor in a subsequent salicide process. Therefore, it is impossible to obtain desired properties of the transistor, and this fact becomes a factor that changes characteristics of a pixel of the image sensor.
It is, therefore, an object of the present invention to provide a method for fabricating an image sensor capable of preventing a salicide layer from being formed on a photodiode as simultaneously as of forming the salicide layer selectively on a gate electrode of a transistor closely located to the photodiode.
In accordance with an aspect of the present invention, there is provided a method for fabricating an image sensor, including the steps of: forming a gate electrode on a substrate; forming an insulating spacer at lateral sides of the gate electrode; forming a photodiode in the substrate exposed at an one edge of the gate electrode; forming a floating diffusion area in the substrate exposed at the other edge of the gate electrode; forming a salicide barrier layer on the photodiode, wherein the salicide barrier layer exposes a upper surface and corners of the gate electrode; and forming a salicide layer on the exposed upper surface and the upper corners of the gate.
In accordance with another aspect of the present invention, there is also provided a method for forming an image sensor, including the steps of: forming a gate electrode on a substrate; forming an insulating spacer at lateral sides of the gate electrode; forming a photodiode in the substrate exposed at one edge of the gate electrode; forming a floating diffusion area in the substrate exposed at the other edge of the gate electrode; forming a salicide barrier layer on the photodiode and the floating diffusion area, wherein the salicide barrier layer exposes an upper surface and upper corners of the gate electrode; removing the salicide barrier layer on the floating diffusion area; and forming a plurality of salicide layers simultaneously formed on the upper surface and upper corners of the gate electrode and the upper surface of the floating diffusion area.